Development Status of InP and CMOS Heterogeneous Integration Technology

Rong chen is an advanced packaging expert at CETC Chip Institute and Head of the Microsystem Integration Group at the National Laboratory of Integrated Circuits and Microsystems. She has led or participated in over ten national and ministerial-level key projects. Her current research is dedicated to 2.5D packaging and Chiplet technologies for high-speed, high-precision mixed-signal circuits, with over 10 publications and 3 patents.

InP and CMOS are two distinct semiconductor materials with its unique advantages and limitations. InP materials feature high electron mobility and high cutoff frequency, making them suitable for high-frequency and optoelectronic device fabrication. CMOS materials offer high electron mobility and high integration density, making them ideal for digital integrated circuits. To achieve frequencies of >100 GHz, the heterogeneous integration of InP and CMOS can offer superior performance and application value. However, there are several technical challenges in the integration process: particularly concerning material compatibility, device interoperability, and manufacturing processes. As a result, the heterogeneous integration of InP and CMOS has become a key area of research in recent years. This paper analyzes the development status of InP and CMOS heterogeneous integration technology, examines the main challenges currently faced by the technology, and explores future development directions, providing strong support for high-frequency (>100 GHz) wireless communications, radar imaging, and other high-performance applications.